In present computer systems, a "halt load" condition typically results when one switches clock generation from one card to another. This typically corrupts the system, causing loss-of-memory (e.g. because related microprocessor etc. is unable to tolerate clock pulses which are stretched or foreshortened)--hence, loss of the application program being run (at the time of failure) and causes system "down-time" because of the "halt load". An example is the arrangement in FIG. 1, with clock-cards #1B, 1B' coupled to switchover circuit 1A.
This invention allows switchover of system clock generation and distribution: from a primary card to a secondary (back-up) card, with no loss of clock and essential pulse-width requirements maintained, giving a switchover which is "transparent" to the system.
This invention also provides a system designed so that loss of power on one clock-generating card (CGC) does not disturb the (connected) circuit operation of a companion CGC.
As a supplemental feature, this invention teaches the possible use of micro-controller means to control such "Dynamic Clock Switch-over", using a clock source which is separate from the system clock, and is independent.
Workers have for some time been concerned with the problem of switching from one clock source to another [e.g. see U.S. Pat. No. 4853653 to Maher for "Multiple Input Clock Selector", but this system must be "halted" before switching clocks; whereupon pulse width is stretched for several clock cycles to avoid generation of short ("runt") pulses--such is not acceptable for systems using a microprocessor, as with this invention, where pulse-width requirements must be maintained.] Also, this invention allows the use of asynchronous clocks, with no analogous problems of stability or anomalous ("runt ") signals.